1. Field of the Invention
The present invention relates generally to the field of semiconductor devices and, more particularly, the present invention relates to an improved CMOS circuit.
Due to the structural miniaturizations in MOS technology, the properties of MOS transistors and CMOS circuits must be maintained through the micrometer range. However, in MOS transistors with channel lengths of, for example, less than 100 nm, short-channel and punch effects occur. These effects can in fact be partially compensated by an increased doping of the substrate, but the required high doping of the substrate results in, among other things, a deterioration of the charge carrier mobility in the channel. Additionally, in MOS transistors with channel lengths less than 100 nm, the subthreshold slope d In(I.sub.drain)/d V.sub.gate must be maximized so that, even at low operating voltages, the currents in the conductive condition and in the non-conductive condition can be clearly distinguished. Finally, in order to avoid extreme short-channel effects, flat source/drain regions must be utilized that exhibit a low specific series resistance on the order of 100 .OMEGA..mu.m.
2. Description of the Related Art
For increasing the charge carrier mobility, it has been proposed in the literature (see, for example, K. Rim et al., IEEE IEDM Tech. Dig., page 517 (1995) to realize n-channel and p-channel transistors in substrates that comprise strained silicon at least in the channel region of the transistors. Strained silicon is silicon whose lattice constant is increased in two spatial directions compared to unstrained silicon. Strained silicon is produced by growing silicon lattice-matched to a substrate having a higher lattice constant. Si.sub.1- Ge.sub.x is suitable as such a substrate material. The high defect densities in the Si.sub.1-x Ge.sub.x substrate is a problem in the manufacture of strained silicon.
It has been proposed (see A. R. Powell et al., Appl. Phys. Lett. 64, page 1856 (1994)) to grow the Si.sub.1-x Ge.sub.x layer on the thinned silicon layer of an SOI substrate. Stresses in the Si.sub.1-x Ge.sub.x layer relax in this case into the thinned silicon layer lying therebelow, insofar as the germanium content in the Si.sub.1-x Ge.sub.x layer is less than 15 percent.
In order to manufacture very flat source/drain regions with low series resistance, Y. Mitani et al., IEEE VLSI Tech. Dig., page 91 (1996), has proposed that the source/drain regions be manufactured by etching depressions into the surface of the substrate and selective, in situ doped growth of amorphous silicon and subsequent recrystallization of the amorphous silicon. However, there are shortcomings to this design as well.
The present invention is based on the problem of providing an integrated CMOS circuit arrangement and a method for the manufacture thereof in which short-channel effects and punch effects are prevented and high charge carrier mobility is assured.